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LTC2440 24-Bit High Speed Differential ADC with Selectable Speed/Resolution
FEATURES

DESCRIPTIO
Up to 3.5kHz Output Rate Selectable Speed/Resolution 2VRMS Noise at 880Hz Output Rate 200nVRMS Noise at 6.9Hz Output Rate with Simultaneous 50/60Hz Rejection 0.0005% INL, No Missing Codes Autosleep Enables 20A Operation at 6.9Hz < 5V Offset (4.5V < VCC < 5.5V, - 40C to 85C) Differential Input and Differential Reference with GND to VCC Common Mode Range No Latency, Each Conversion is Accurate Even After an Input Step Internal Oscillator--No External Components Pin Compatible with the LTC2410 24-Bit ADC in Narrow 16-Lead SSOP Package
The LTC(R)2440 is a high speed 24-bit No Latency TM ADC with 5ppm INL and 5V offset. It uses proprietary deltasigma architecture enabling variable speed and resolution with no latency. Ten speed/resolution combinations (6.9Hz/ 200nVRMS to 3.5kHz/25VRMS) are programmed through a simple serial interface. Alternatively, by tying a single pin HIGH or LOW, a fast (880Hz/2VRMS) or ultralow noise (6.9Hz, 200nVRMS, 50/60Hz rejection) speed/resolution combination can be easily selected. The accuracy (offset, full-scale, linearity, drift) and power dissipation are independent of the speed selected. Since there is no latency, a speed/resolution change may be made between conversions with no degradation in performance. Following each conversion cycle, the LTC2440 automatically enters a low power sleep state. Power dissipation may be reduced by increasing the duration of this sleep state. For example, running at the 3.5kHz conversion speed but reading data at a 100Hz rate draws 240A average current (1.1mW) while reading data at a 7Hz output rate draws only 25A (125W).The LTC2440 communicates through a flexible 3-wire or 4-wire digital interface that is compatible with the LTC2410 and is available in a narrow 16-lead SSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation. No Latency is a trademark of Linear Technology Corporation.
APPLICATIO S

High Speed Multiplexing Weight Scales Auto Ranging 6-Digit DVMs Direct Temperature Measurement High Speed Data Acquisition
TYPICAL APPLICATIO
4.5V TO 5.5V
Simple 24-Bit 2-Speed Acquisition System
100 VCC = 5V VREF = 5V VIN+ = VIN- = 0V
VCC
BUSY
RMS NOISE (V)
2 3 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT -0.5VREF TO 0.5VREF 4 5 6
15
10 2V AT 880Hz 200nV AT 6.9Hz 1 (50/60Hz REJECTION)
1, 8, 9, 16
LTC2440 14 FO REF + 13 REF - SCK 12 IN + SDO 11 IN - CS 7 SDI 10 EXT GND
3-WIRE SPI INTERFACE
VCC 6.9Hz, 200nV NOISE, 50/60Hz REJECTION 10-SPEED SERIAL PROGRAMMABLE 880Hz OUTPUT RATE, 2V NOISE
0.1 1 10 100 1000 CONVERSION RATE (Hz) 10000
2440 TA02
2440 TA01 2440 TA01
U
Speed vs RMS Noise
sn2440, 2440fas
U
U
1
LTC2440
ABSOLUTE
(Notes 1, 2)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW GND VCC REF + REF - IN + IN - SDI GND 1 2 3 4 5 6 7 8 16 GND 15 BUSY 14 FO 13 SCK 12 SDO 11 CS 10 EXT 9 GND
Supply Voltage (VCC) to GND .......................- 0.3V to 6V Analog Input Pins Voltage to GND .................................... - 0.3V to (VCC + 0.3V) Reference Input Pins Voltage to GND .................................... - 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ - 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... - 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2440C ............................................... 0C to 70C LTC2440I ............................................ - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC2440CGN LTC2440IGN
GN PART MARKING 2440 2440I
GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125C, JA = 110C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3, 4)
PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Total Unadjusted Error CONDITIONS 0.1V VREF VCC, -0.5 * VREF VIN 0.5 * VREF, (Note 5) VCC = 5V, REF+ = 5V, REF- = GND, VINCM = 2.5V, (Note 6) REF+ = 2.5V, REF- = GND, VINCM = 1.25V, (Note 6) 2.5V REF+ VCC, REF- = GND, GND IN+ = IN- VCC (Note 12) 2.5V REF+ VCC, REF- = GND, GND IN+ = IN- VCC REF + = 5V, REF - = GND, IN + = 3.75V, IN - = 1.25V REF + = 2.5V, REF - = GND, IN + = 1.875V, IN - = 0.625V 2.5V REF+ VCC, REF- = GND, IN+ = 0.75REF+, IN- = 0.25 * REF+ REF + = 5V, REF - = GND, IN + = 1.25V, IN - = 3.75V REF + = 2.5V, REF - = GND, IN + = 0.625V, IN - = 1.875V 2.5V REF+ VCC, REF- = GND, IN+ = 0.25 * REF+, IN- = 0.75 * REF+ 5V VCC 5.5V, REF+ = 2.5V, REF- = GND, VINCM = 1.25V 5V VCC 5.5V, REF+ = 5V, REF- = GND, VINCM = 2.5V REF+ = 2.5V, REF- = GND, VINCM = 1.25V, (Note 6) 2.5V REF+ VCC, REF- = GND, GND IN- = IN+ VCC

ELECTRICAL CHARACTERISTICS
MIN 24
TYP 5 3 2.5 20 10 10 0.2 10 10 0.2 15 15 15 120
MAX 15 5
UNITS Bits ppm of VREF ppm of VREF V nV/C
30 50
ppm of VREF ppm of VREF ppm of VREF/C
30 50
ppm of VREF ppm of VREF ppm of VREF/C ppm of VREF ppm of VREF ppm of VREF dB
Input Common Mode Rejection DC
sn2440, 2440fas
2
U
W
U
U
WW
W
LTC2440
A ALOG I PUT A D REFERE CE The denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C. (Note 3)
SYMBOL IN+ IN- VIN REF+ REF- VREF CS(IN+) CS(IN-) CS(REF+) CS(REF-) IDC_LEAK(IN+, IN-,
REF+, REF-)
PARAMETER Absolute/Common Mode IN+ Voltage Absolute/Common Mode IN- Voltage Input Differential Voltage Range (IN+ - IN-) Absolute/Common Mode REF+ Voltage Absolute/Common Mode REF- Voltage Reference Differential Voltage Range (REF+ - REF-) IN+ Sampling Capacitance IN- Sampling Capacitance REF+ Sampling Capacitance REF- Sampling Capacitance Leakage Current, Inputs and Reference Average Input/Reference Current During Sampling
ISAMPLE(IN+, IN-,
REF+, REF-)
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL VIH VIL VIH VIL IIN IIN CIN CIN VOH VOL VOH VOL IOZ PARAMETER High Level Input Voltage CS, FO Low Level Input Voltage CS, FO High Level Input Voltage SCK Low Level Input Voltage SCK Digital Input Current CS, FO Digital Input Current SCK Digital Input Capacitance CS, FO Digital Input Capacitance SCK High Level Output Voltage SDO, BUSY Low Level Output Voltage SDO, BUSY High Level Output Voltage SCK Low Level Output Voltage SCK Hi-Z Output Leakage SDO (Note 8) IO = -800A IO = 1.6mA IO = -800A (Note 9) IO = 1.6mA (Note 9) CONDITIONS 4.5V VCC 5.5V 4.5V VCC 5.5V
The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
MIN

4.5V VCC 5.5V (Note 8) 4.5V VCC 5.5V (Note 8) 0V VIN VCC 0V VIN VCC (Note 8)
U
U
U
U
U
U
CONDITIONS

MIN GND - 0.3V GND - 0.3V -VREF/2 0.1 GND 0.1
TYP
MAX VCC + 0.3V VCC + 0.3V VREF/2 VCC VCC - 0.1V VCC
UNITS V V V V V V pF pF pF pF
3.5 3.5 3.5 3.5 CS = VCC, IN+ = GND, IN- REF+ = 5V, REF- = GND = GND,
-100
10
100
nA
Varies, See Applications Section
TYP
MAX
UNITS V
2.5 0.8 2.5 0.8 -10 -10 10 10 10 10
V V V A A pF pF V

VCC - 0.5V 0.4V VCC - 0.5V 0.4V -10 10
V V V A
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LTC2440
POWER REQUIRE E TS
SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Mode Sleep Mode CS = 0V (Note 7) CS = VCC (Note 7)
The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS

TI I G CHARACTERISTICS
SYMBOL fEOSC tHEO tLEO tCONV PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time
The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS

fISCK DISCK fESCK tLESCK tHESCK tDOUT_ISCK tDOUT_ESCK t1 t2 t3 t4 tKQMAX tKQMIN t5 t7 t8
Internal SCK Frequency Internal SCK Duty Cycle External SCK Frequency Range External SCK Low Period External SCK High Period Internal SCK 32-Bit Data Output Time External SCK 32-Bit Data Output Time CS to SDO Low Z CS to SDO High Z CS to SCK CS to SCK SCK to SDO Valid SDO Hold After SCK SCK Set-Up Before CS SDI Setup Before SCK SDI Hold After SCK
Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: VCC = 4.5 to 5.5V unless otherwise specified. VREF = REF + - REF -, VREFCM = (REF + + REF -)/2; VIN = IN + - IN -, VINCM = (IN + + IN -)/2. Note 4: FO pin tied to GND or to external conversion clock source with fEOSC = 10MHz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
4
UW
MIN 4.5
TYP
MAX 5.5
UNITS V mA A
8 8
11 30
UW
MIN 0.1 25 25 0.99 126
TYP
MAX 20 10000 10000
UNITS MHz ns ns ms ms ms
OSR = 256 (SDI = 0) OSR = 32768 (SDI = 1) External Oscillator (Note 10, 13) Internal Oscillator (Note 9) External Oscillator (Notes 9, 10) (Note 9) (Note 8) (Note 8) (Note 8) Internal Oscillator (Notes 9, 11) External Oscillator (Notes 9, 10) (Note 8) (Note 12) (Note 12) (Note 9) (Notes 8, 12) (Note 5)

1.13 145
1.33 170
40 * OSR + 170 fEOSC(kHz)
0.8 45 25 25 41.6 35.3 320/fEOSC 32/fESCK 0 0 5 25 25 15 50 10 10 Note 5 Note 5 25 25 30.9 0.9 fEOSC/10 1 55 20
MHz Hz % MHz ns ns s s s ns ns s ns ns ns ns ns ns
Note 7: The converter uses the internal oscillator. Note 8: The converter is in external SCK mode of operation such that the SCK pin is used as a digital input. The frequency of the clock signal driving SCK during the data output is fESCK and is expressed in Hz. Note 9: The converter is in internal SCK mode of operation such that the SCK pin is used as a digital output. In this mode of operation, the SCK pin has a total equivalent load capacitance of CLOAD = 20pF. Note 10: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 11: The converter uses the internal oscillator. FO = 0V. Note 12: Guaranteed by design and test correlation. Note 13: There is an internal reset that adds an additional 1s (typical) to the conversion time.
sn2440, 2440fas
LTC2440 TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity fOUT = 3.5kHz
10 VCC = 5V VREF = 5V VREF+ = 5V - 5 VREF = GND VINCM = 2.5V FO = GND TA = 25C
INL ERROR (ppm OF VREF)
INL ERROR (ppm OF VREF)
0
0
INL ERROR (ppm OF VREF)
-5
-10 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 VIN (V)
Integral Nonlinearity fOUT = 440Hz
10 VCC = 5V VREF = 5V VREF+ = 5V - 5 VREF = GND VINCM = 2.5V FO = GND TA = 25C INL ERROR (ppm OF VREF) 10
INL ERROR (ppm OF VREF)
INL ERROR (ppm OF VREF)
0
-5
-10 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 VIN (V)
Integral Nonlinearity fOUT = 55Hz
10 VCC = 5V VREF = 5V VREF+ = 5V - 5 VREF = GND VINCM = 2.5V FO = GND TA = 25C
INL ERROR (ppm OF VREF)
10
INL ERROR (ppm OF VREF)
0
0
INL ERROR (ppm OF VREF)
-5
-10 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 VIN (V)
UW
1.5 2
2440 G01
Integral Nonlinearity fOUT = 1.76kHz
10 VCC = 5V VREF = 5V VREF+ = 5V - 5 VREF = GND VINCM = 2.5V FO = GND TA = 25C
10
Integral Nonlinearity fOUT = 880Hz
VCC = 5V VREF = 5V VREF+ = 5V - 5 VREF = GND VINCM = 2.5V FO = GND TA = 25C
0
-5
-5
2.5
-10 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 VIN (V)
1.5 2 2.5
2440 G02
-10 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 VIN (V)
1.5 2
2.5
2440 G03
Integral Nonlinearity fOUT = 220Hz
VCC = 5V VREF = 5V VREF+ = 5V - 5 VREF = GND VINCM = 2.5V FO = GND TA = 25C
10
Integral Nonlinearity fOUT = 110Hz
VCC = 5V VREF = 5V VREF+ = 5V - 5 VREF = GND VINCM = 2.5V FO = GND TA = 25C
0
0
-5
-5
1.5 2
2.5
-10 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 VIN (V)
1.5 2
2.5
-10 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 VIN (V)
1.5 2
2.5
2440 G04
2440 G05
2440 G06
Integral Nonlinearity fOUT = 27.5Hz
VCC = 5V VREF = 5V VREF+ = 5V - 5 VREF = GND VINCM = 2.5V FO = GND TA = 25C 10
Integral Nonlinearity fOUT = 13.75Hz
VCC = 5V VREF = 5V VREF+ = 5V - 5 VREF = GND VINCM = 2.5V FO = GND TA = 25C
0
-5
-5
1.5 2 2.5
2440 G07
-10 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 VIN (V)
1.5 2
2.5
-10 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 VIN (V)
1.5 2
2.5
2440 G08
2440 G09
sn2440, 2440fas
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LTC2440 TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity fOUT = 6.875Hz
10 VCC = 5V VREF = 5V VREF+ = 5V - 5 VREF = GND VINCM = 2.5V FO = GND TA = 25C
10.0
INL ERROR (ppm OF VREF)
INL ERROR (ppm OF VREF)
INL ERROR (ppm OF VREF)
0
-5
-10 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 VIN (V)
Integral Nonlinearity vs Temperature
10 VCC = 5V VREF = 2.5V VREF+ = 2.5V - 5 VREF = GND VINCM = 1.25V OSR = 32768 FO = GND 10
-FULL-SCALE ERROR (ppm OF VREF)
INL ERROR (ppm OF VREF)
INL ERROR (ppm OF VREF)
TA = -55C 0 TA = 25C -5
TA = 125C
-10 -1.25
-0.75
0.25 -0.25 VIN (V)
+Full-Scale Error vs VREF
20 10
+FULL-SCALE ERROR (ppm OF VREF)
FULL-SCALE ERROR (ppm OF VREF)
10
8 7 6 5 4 3 VREF = 2.5V 2 VREF+ = 2.5V - 1 VREF = GND VINCM = 1.25V 0 4.7 4.5 OSR = 32768 FO = GND TA = 25C 5.1 4.9 VCC (V) 5.3 5.5
2440 G17
FULL-SCALE ERROR (ppm OF VREF)
0
-10
-20
0
1
3 2 VREF (V)
6
UW
2440 G10
Integral Nonlinearity vs Conversion Rate
VCC = 5V VREF = 5V VREF+ = 5V VREF- = GND -2.5V VIN 2.5V VINCM = 2.5V FO = GND TA = 25C
Integral Nonlinearity vs VINCM
10 VINCM = 3.75V 5 VINCM = 2.5V 0 VINCM = 1.25V -5 VCC = 5V OSR = 32768 FO = GND VREF = 2.5V VREF+ = 2.5V TA = 25C VREF- = GND -10 -0.75 -0.25 0.25 -1.25 VIN (V)
7.5
5.0
2.5
0
1.5 2 2.5
0
500
1000 1500 2000 2500 3000 3500 CONVERSION RATE (Hz)
2440 G11
0.75
1.25
2440 G12
Integral Nonlinearity vs Temperature
VCC = 5V VREF = 5V VREF+ = 5V - 5 VREF = GND VINCM = 2.5V OSR = 32768 FO = GND 20
-Full-Scale Error vs VREF
10
0
TA = 125C
0
TA = -25C -5
TA = 25C
-10
0.75
1.25
2440 G13
-10 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 VIN (V)
1.5 2
2.5
-20
0
1
3 2 VREF (V)
4
5
2440 G15
2440 G14
-Full-Scale Error vs VCC
0 9
+Full-Scale Error vs VCC
OSR = 32768 VREF = 2.5V -1 VREF+ = 2.5V FO = GND - = GND T = 25C V -2 VREF = 1.25V A INCM -3 -4 -5 -6 -7 -8 -9 -10 4.5 4.7 5.1 4.9 VCC (V) 5.3 5.5
2440 G18
4
5
2440 G16
sn2440, 2440fas
LTC2440 TYPICAL PERFOR A CE CHARACTERISTICS
Negative Full-Scale Error vs Temperature
20
FULL-SCALE ERROR (ppm OF VREF)
FULL-SCALE ERROR (ppm OF VREF)
15 10 4.5V 5 0 -5 -10 -15 -20 -55 -25 5.5V 5V
10 5 0 -5 4.5V -10 -15 -20 -55 -25 5V VCC = 4.5V VREF = 4.5V VREF+ = 4.5V VREF- = GND VINCM = 2.25V OSR = 32768 FO = GND VCC = 5.5V, 5V VREF = 5V VREF+ = 5V VREF- = GND VINCM = 2.5V OSR = 32768 FO = GND 95 125
2440 G20
5.5V
OFFSET ERROR (ppm OF VREF)
VCC = 4.5V VREF = 4.5V VREF+ = 4.5V VREF- = GND VINCM = 2.25V OSR = 32768 FO = GND
VCC = 5.5V, 5V VREF = 5V VREF+ = 5V VREF- = GND VINCM = 2.5V OSR = 32768 FO = GND
35 5 65 TEMPERATURE (C)
Offset Error vs Conversion Rate
VCC = 5V VREF = 5V VREF+ = 5V - 2.5 VREF = GND 5.0 VIN+ = VIN- = GND FO = GND TA = 25C
5.0
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
0
RMS NOISE (V)
-2.5
-5.0 0 500 1000 1500 2000 2500 3000 3500 CONVERSION RATE (Hz)
2440 G22
Offset Error vs Temperature
5.0 20 18 2.5 LINEARITY (BITS) VCC = 5V 0 VCC = 4.5V VREF = 2.5V VREF+ = 2.5V VREF- = GND VIN+ = VIN- = GND OSR = 256 FO = GND -25 VCC = 5.5V, 5V VREF = 5V VREF+ = 5V VREF- = GND VIN+ = VIN- = GND OSR = 256 FO = GND 95 125
2440 G25
OFFSET ERROR (V)
VCC = 5.5V
VCC = 4.5V
12 10 8 6 4 2
EXTERNAL CLOCK 10MHz (OR INTERNAL OSCILLATOR) EXTERNAL CLOCK 20MHz
RMS NOISE (V)
-2.5
-5.0 -55
5 35 65 TEMPERATURE (C)
UW
95
2440 G19
Positive Full-Scale Error vs Temperature
20 15
5.0
Offset Error vs VCC
VREF = 2.5V VREF+ = 2.5V VREF- = GND + - 2.5 VIN = VIN = GND OSR = 32768 FO = GND TA = 25C
0
-2.5
125
35 5 65 TEMPERATURE (C)
-5.0 4.5
4.7
5.1 4.9 VCC (V)
5.3
5.5
2440 G21
Offset Error vs VINCM
VCC = 5V VREF = 5V VREF+ = 5V - 2.5 VREF = GND VIN+ = VIN- = VINCM OSR = 32768 FO = GND TA = 25C
RMS Noise vs Temperature
3.5 3.0 2.5 2.0 1.5 1.0 VCC = 4.5V VREF = 2.5V VREF+ = 2.5V VREF- = GND VIN+ = VIN- = GND OSR = 256 FO = GND -25 VCC = 5.5V, 5V VREF = 5V VREF+ = 5V VREF- = GND VIN+ = VIN- = GND OSR = 256 FO = GND 95 125
2440 G24
VCC = 4.5V VCC = 5V VCC = 5.5V
0
-2.5
-5.0
0
1
3 2 VINCM (V)
4
5
2440 G23
0.5 -55
5 35 65 TEMPERATURE (C)
INL vs Output Rate (OSR = 128) External Clock Sweep 10MHz to 20MHz
5
RMS Noise vs Output Rate (OSR = 128) External Clock Sweep 10MHz to 20MHz
16 14
4
3
2
VREF = VCC = 5V TEMP = 25C SWEEP (VIN - VREF/2) TO VREF/2 2500 3000 3500 OUTPUT RATE (Hz) 4000
2440 G26
1
VREF = VCC = 5V TEMP = 25C VIN VREF/2 2500 3000 3500 OUTPUT RATE (Hz) 4000
2440 G27
0 2000
0 2000
sn2440, 2440fas
7
LTC2440
PI FU CTIO S
GND (Pins 1, 8, 9, 16): Ground. Multiple ground pins internally connected for optimum ground current flow and VCC decoupling. Connect each one of these pins to a ground plane through a low impedance connection. All four pins must be connected to ground for proper operation. VCC (Pin 2): Positive Supply Voltage. Bypass to GND (Pin 1) with a 10F tantalum capacitor in parallel with 0.1F ceramic capacitor as close to the part as possible. REF + (Pin 3), REF - (Pin 4): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF +, is maintained more positive than the reference negative input, REF -, by at least 0.1V. IN + (Pin 5), IN - (Pin 6): Differential Analog Input. The voltage on these pins can have any value between GND - 0.3V and VCC + 0.3V. Within these limits the converter bipolar input range (VIN = IN+ - IN-) extends from - 0.5 * (VREF ) to 0.5 * (VREF ). Outside this input range the converter produces unique overrange and underrange output codes. SDI (Pin 7): Serial Data Input. This pin is used to select the speed/resolution of the converter. If SDI is grounded (pin compatible with LTC2410) the device outputs data at 880Hz with 21 bits effective resolution. By tying SDI HIGH, the converter enters the ultralow noise mode (200nVRMS) with simultaneous 50/60Hz rejection at 6.9Hz output rate. SDI may be driven logic HIGH or LOW anytime during the conversion or sleep state in order to change the speed/resolution. The conversion immediately following the data output cycle will be valid and performed at the newly selected output rate/resolution. SDI may also be programmed by a serial input data stream under control of SCK during the data output cycle. One of ten speed/resolution ranges (from 6.9Hz/200nVRMS to 3.5kHz/21VRMS) may be selected. The first conversion following a new selection is valid and performed at the newly selected speed/resolution. EXT (Pin 10): Internal/External SCK Selection Pin. This pin is used to select internal or external SCK for outputting data. If EXT is tied low (pin compatible with the LTC2410), the device is in the external SCK mode and data is shifted out the device under the control of a user applied serial clock. If EXT is tied high, the internal serial clock mode is selected. The device generates its own SCK signal and outputs this on the SCK pin. A framing signal BUSY (Pin 15) goes low indicating data is being output. CS (Pin 11): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. Following each conversion the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion. SDO (Pin 12): Three-State Digital Output. During the Data Output period, this pin is used as serial data output. When the chip select CS is HIGH (CS = VCC) the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW. SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal Serial Clock Operation mode, SCK is used as digital output for the internal serial interface clock during the Data Output period. In External Serial Clock Operation mode, SCK is used as digital input for the external serial interface clock during the Data Output period. The Serial Clock Operation mode is determined by the logic level applied to the EXT pin. FO (Pin 14): Frequency Control Pin. Digital input that controls the internal conversion clock. When FO is connected to VCC or GND, the converter uses its internal oscillator running at 9MHz. The conversion rate is determined by the selected OSR such that tCONV (in ms) = (40 * OSR + 170)/ 9000 (tCONV = 1.137ms at OSR = 256, tCONV = 146ms at OSR = 32768). The first null is located at 8/tCONV, 7kHz at OSR = 256 and 55Hz (simultaneous 50/60Hz) at OSR = 32768. When FO is driven by an oscillator with frequency fEOSC (in kHz), the conversion time becomes tCONV = (40 * OSR + 170)/fEOSC (in ms) and the first null remains 8/tCONV. BUSY (Pin 15): Conversion in Progress Indicator. For compatibility with the LTC2410, this pin should not be tied to ground. This pin is HIGH while the conversion is in progress and goes LOW indicating the conversion is complete and data is ready. It remains low during the sleep and data output states. At the conclusion of the data output state, it goes HIGH indicating a new conversion has begun.
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LTC2440
FU CTIO AL BLOCK DIAGRA
VCC GND AUTOCALIBRATION AND CONTROL
IN + IN -
+ -

ADC SERIAL INTERFACE
DAC
+-
REF + REF -
Figure 1. Functional Block Diagram
TEST CIRCUITS
SDO 1.69k CLOAD = 20pF
SDO
Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z
2440 TA03
APPLICATIO S I FOR ATIO
CONVERTER OPERATION Converter Operation Cycle
The LTC2440 is a high speed, delta-sigma analog-todigital converter with an easy to use 4-wire serial interface (see Figure 1). Its operation is made up of three states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see Figure 2). The 4-wire interface consists of serial data input (SDI), serial data output (SDO), serial clock (SCK) and chip select (CS). The interface, timing,
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INTERNAL OSCILLATOR FO (INT/EXT) SDO SCK CS SDI BUSY
2440 F01
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DECIMATING FIR
EXT
VCC 1.69k
CLOAD = 20pF
Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z
2440 TA04
CONVERT
SLEEP
FALSE
CS = LOW AND SCK TRUE DATA OUTPUT
2440 F02
Figure 2. LTC2440 State Transition Diagram
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LTC2440
APPLICATIO S I FOR ATIO
operation cycle and data out format is compatible with the LTC2410. Initially, the LTC2440 performs a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, power consumption is reduced below 10A. The part remains in the sleep state as long as CS is HIGH. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state. Once CS is pulled LOW, the device begins outputting the conversion result. There is no latency in the conversion result. The data output corresponds to the conversion just performed. This result is shifted out on the serial data out pin (SDO) under the control of the serial clock (SCK). Data is updated on the falling edge of SCK allowing the user to reliably latch data on the rising edge of SCK (see Figure 3). The data output state is concluded once 32-bits are read out of the ADC or when CS is brought HIGH. The device automatically initiates a new conversion and the cycle repeats. Through timing control of the CS, SCK and EXT pins, the LTC2440 offers several flexible modes of operation (internal or external SCK). These various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section. Ease of Use The LTC2440 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog voltages is easy. Speed/resolution adjustments may be made seamlessly between two conversions without settling errors. The LTC2440 performs offset and full-scale calibrations every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift.
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Power-Up Sequence The LTC2440 automatically enters an internal reset state when the power supply voltage VCC drops below approximately 2.2V. This feature guarantees the integrity of the conversion result and of the serial interface mode selection. When the VCC voltage rises above this critical threshold, the converter creates an internal power-on-reset (POR) signal with a duration of approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2440 starts a normal conversion cycle and follows the succession of states described above. The first conversion result following POR is accurate within the specifications of the device if the power supply voltage is restored within the operating range (4.5V to 5.5V) before the end of the POR time interval. Reference Voltage Range This converter accepts a truly differential external reference voltage. The absolute/common mode voltage specification for the REF + and REF - pins covers the entire range from GND to VCC. For correct converter operation, the REF + pin must always be more positive than the REF - pin. The LTC2440 can accept a differential reference voltage from 0.1V to VCC. The converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in microvolts is nearly constant with reference voltage. A decrease in reference voltage will not significantly improve the converter's effective resolution. On the other hand, a reduced reference voltage will improve the converter's overall INL performance. Input Voltage Range The analog input is truly differential with an absolute/ common mode range for the IN+ and IN- input pins extending from GND - 0.3V to VCC + 0.3V. Outside these limits, the ESD protection devices begin to turn on and the errors due to input leakage current increase rapidly. Within these limits, the LTC2440 converts the bipolar differential input signal, VIN = IN+ - IN-, from - FS = - 0.5 * VREF to +FS = 0.5 * VREF where VREF =
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LTC2440
APPLICATIO S I FOR ATIO
REF+ - REF-. Outside this range, the converter indicates the overrange or the underrange condition using distinct output codes. Output Data Format The LTC2440 serial output data stream is 32-bits long. The first 3-bits represent status information indicating the sign and conversion state. The next 24-bits are the conversion result, MSB first. The remaining 5-bits are sub LSBs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. In the case of ultrahigh resolution modes, more than 24 effective bits of performance are possible (see Table 3). Under these conditions, sub LSBs are included in the conversion result and represent useful information beyond the 24-bit level. The third and fourth bit together are also used to indicate an underrange condition (the differential input voltage is below -FS) or an overrange condition (the differential input voltage is above +FS). For input conditions in excess of twice full scale (|VIN| VREF), the converter may indicate either overrange or underrange. Once the input returns to the normal operating range, the conversion result is immediately accurate within the specifications of the device. Bit 31 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CS pin is LOW. This bit is HIGH during the conversion and goes LOW when the conversion is complete. Bit 30 (second output bit) is a dummy bit (DMY) and is always LOW. Bit 29 (third output bit) is the conversion result sign
CS
BIT 31 SDO Hi-Z EOC
BIT 30 "0"
BIT 29 SIG
SCK
1
2
BUSY
2440 F03
SLEEP
Figure 3. Output Data Timing
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indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this bit is LOW. Bit 28 (fourth output bit) is the most significant bit (MSB) of the result. This bit in conjunction with Bit 29 also provides the underrange or overrange indication. If both Bit 29 and Bit 28 are HIGH, the differential input voltage is above +FS. If both Bit 29 and Bit 28 are LOW, the differential input voltage is below -FS. The function of these bits is summarized in Table 1.
Table 1. LTC2440 Status Bits
Input Range VIN 0.5 * VREF 0V VIN < 0.5 * VREF -0.5 * VREF VIN < 0V VIN < - 0.5 * VREF Bit 31 Bit 30 Bit 29 Bit 28 EOC DMY SIG MSB 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0
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Bits ranging from 28 to 5 are the 24-bit conversion result MSB first. Bit 5 is the Least Significant Bit (LSB). Bits ranging from 4 to 0 are sub LSBs below the 24-bit level. Bits 4 to bit 0 may be included in averaging or discarded without loss of resolution. Data is shifted out of the SDO pin under control of the serial clock (SCK), see Figure 3. Whenever CS is HIGH, SDO remains high impedance. In order to shift the conversion result out of the device, CS must first be driven LOW. EOC is seen at the SDO pin of the device once CS is pulled LOW. EOC changes real time from HIGH to LOW at the completion of a conversion. This
BIT 28 MSB
BIT 27
BIT 5 LSB24
BIT 0
3
4
5
26
27
32
DATA OUTPUT
CONVERSION
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LTC2440
APPLICATIO S I FOR ATIO
signal may be used as an interrupt for an external microcontroller. Bit 31 (EOC) can be captured on the first rising edge of SCK. Bit 30 is shifted out of the device on the first falling edge of SCK. The final data bit (Bit 0) is shifted out on the falling edge of the 31st SCK and may be latched on the rising edge of the 32nd SCK pulse. On the falling edge of the 32nd SCK pulse, SDO goes HIGH indicating the initiation of a new conversion cycle. This bit serves as EOC (Bit 31) for the next conversion cycle. Table 2 summarizes the output data format. As long as the voltage on the IN+ and IN- pins is maintained within the - 0.3V to (VCC + 0.3V) absolute maximum operating range, a conversion result is generated for any differential input voltage VIN from -FS = -0.5 * VREF to +FS = 0.5 * VREF. For differential input voltages greater than +FS, the conversion result is clamped to the value corresponding to the +FS + 1LSB. For differential input voltages below -FS, the conversion result is clamped to the value corresponding to -FS - 1LSB. SERIAL INTERFACE PINS The LTC2440 transmits the conversion results and receives the start of conversion command through a synchronous 2-wire, 3-wire or 4-wire interface. During the conversion and sleep states, this interface can be used to assess the converter status and during the data output state it is used to read the conversion result and program the speed/resolution.
Table 2. LTC2440 Output Data Format
Differential Input Voltage VIN * VIN* 0.5 * VREF** 0.5 * VREF** - 1LSB 0.25 * VREF** 0.25 * VREF** - 1LSB 0 -1LSB - 0.25 * VREF** - 0.25 * VREF** - 1LSB - 0.5 * VREF** VIN* < -0.5 * VREF** Bit 31 EOC 0 0 0 0 0 0 0 0 0 0 Bit 30 DMY 0 0 0 0 0 0 0 0 0 0 Bit 29 SIG 1 1 1 1 1 0 0 0 0 0 Bit 28 MSB 1 0 0 0 0 1 1 1 1 0 Bit 27 0 1 1 0 0 1 1 0 0 1 Bit 26 0 1 0 1 0 1 0 1 0 1 Bit 25 0 1 0 1 0 1 0 1 0 1 ... ... ... ... ... ... ... ... ... ... ... Bit 0 0 1 0 1 0 1 0 1 0 1
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*The differential input voltage VIN = IN+ - IN-. **The differential reference voltage VREF = REF+ - REF-.
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Serial Clock Input/Output (SCK) The serial clock signal present on SCK (Pin 13) is used to synchronize the data transfer. Each bit of data is shifted out the SDO pin on the falling edge of the serial clock. In the Internal SCK mode of operation, the SCK pin is an output and the LTC2440 creates its own serial clock. In the External SCK mode of operation, the SCK pin is used as input. The internal or external SCK mode is selected by tying EXT (Pin 10) LOW for external SCK and HIGH for internal SCK. Serial Data Output (SDO) The serial data output pin, SDO (Pin 12), provides the result of the last conversion as a serial bit stream (MSB first) during the data output state. In addition, the SDO pin is used as an end of conversion indicator during the conversion and sleep states. When CS (Pin 11) is HIGH, the SDO driver is switched to a high impedance state. This allows sharing the serial interface with other devices. If CS is LOW during the convert or sleep state, SDO will output EOC. If CS is LOW during the conversion phase, the EOC bit appears HIGH on the SDO pin. Once the conversion is complete, EOC goes LOW. The device remains in the sleep state until the first rising edge of SCK occurs while CS = LOW.
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LTC2440
APPLICATIO S I FOR ATIO
Chip Select Input (CS) The active LOW chip select, CS (Pin 11), is used to test the conversion status and to enable the data output transfer as described in the previous sections. In addition, the CS signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. The LTC2440 will abort any serial data transfer in progress and start a new conversion cycle anytime a LOW-to-HIGH transition is detected at the CS pin after the converter has entered the data output state (i.e., after the fifth falling edge of SCK occurs with CS = LOW). Serial Data Input (SDI)--Logic Level Speed Selection The serial data input (SDI, Pin 7) is used to select the speed/resolution of the LTC2440. A simple 2-speed control is selectable by either driving SDI HIGH or LOW. If SDI is grounded (pin compatible with LTC2410) the device outputs data at 880Hz with 21 bits effective resolution. By tying SDI HIGH, the converter enters the ultralow noise mode (200nVRMS) with simultaneous 50/60Hz rejection at 6.9Hz output rate. SDI may be driven logic HIGH or LOW anytime during the conversion or sleep state in order to change the speed/resolution. The conversion immediately following the data output cycle will be valid and performed at the newly selected output rate/resolution. Changing SDI logic state during the data output cycle should be avoided as speed resolution other than 6.9Hz or 880Hz may be selected. For example, if SDI is changed from logic 0 to logic 1 after the second rising edge of SCK, the conversion rate will change from 880Hz to 55Hz (the following values are listed in Table 3: OSR4 = 0, OSR3 = 0, OSR2 = 1, OSR1 = 1 and OSR0 = 1). If SDI remains HIGH, the conversion rate will switch to the desired 6.9Hz speed immediately following the conversion at 55Hz. The 55Hz rate conversion cycle will be a valid result as well as the first 6.9Hz result. On the other hand, if SDI is changed to a 1 anytime before the first rising edge of SCK, the following conversion rate will become 6.9Hz. If SDI is changed to a 1 after the 5th rising edge of SCK, the next conversion will remain 880Hz while all subsequent conversions will be at 6.9Hz.
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Serial Data Input (SDI)--Serial Input Speed Selection SDI may also be programmed by a serial input data stream under control of SCK during the data output cycle, see Figure 4. One of ten speed/resolution ranges (from 6.9Hz/ 200nVRMS to 3.5kHz/21VRMS) may be selected, see Table 3. The conversion following a new selection is valid and performed at the newly selected speed/resolution. BUSY The BUSY output (Pin 15) is used to monitor the state of conversion, data output and sleep cycle. While the part is converting, the BUSY pin is HIGH. Once the conversion is complete, BUSY goes LOW indicating the conversion is complete and data out is ready. The part now enters the LOW power sleep state. BUSY remains LOW while data is shifted out of the device. It goes HIGH at the conclusion of the data output cycle indicating a new conversion has begun. This rising edge may be used to flag the completion of the data read cycle. SERIAL INTERFACE TIMING MODES The LTC2440's 2-wire, 3-wire or 4-wire interface is SPI and MICROWIRE compatible. This interface offers several flexible modes of operation. These include internal/external serial clock, 2-wire or 3-wire I/O, single cycle conversion and autostart. The following sections describe each of these serial interface timing modes in detail. In all these cases, the converter can use the internal oscillator (FO = LOW) or an external oscillator connected to the FO pin. See Table 4 for a summary. External Serial Clock, Single Cycle Operation (SPI/MICROWIRE Compatible) This timing mode uses an external serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 5. The serial clock mode is selected by the EXT pin. To select the external serial clock mode, EXT must be tied low. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. While CS is pulled LOW, EOC is output to the SDO pin.
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APPLICATIO S I FOR ATIO
CS
SCK
SDI
OSR4* BIT 31 Hi-Z
OSR3 BIT 30 "0"
OSR2 BIT 29 SIG
SDO
EOC
BUSY
2440 F04
*OSR4 BIT MUST BE AT FIRST SCK RISING EDGE DURING SERIAL DATA OUT CYCLE
Figure 4. SDI Speed/Resolution Programming
Table 3. SDI Speed/Resolution Programming
CONVERSION RATE INTERNAL EXTERNAL RMS OSR4 OSR3 OSR2 OSR1 OSR0 9MHz CLOCK 10.24MHz CLOCK NOISE ENOB X X 0 X X X X X X X X 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 3.52kHz 1.76kHz 880Hz 880Hz 440Hz 220Hz 110Hz 55Hz 27.5Hz 13.75Hz 6.875Hz 4kHz 2kHz 1kHz 1kHz 500Hz 250Hz 125Hz 62.5Hz 31.25Hz 15.625Hz 7.8125Hz 23V 3.5V 2V 2V 1V 17 20 21.3 21.3 22.4
**Address allows tying SDI HIGH *Additional address to allow tying SDI LOW
Table 4. LTC2440 Interface Timing Modes
SCK Source External External Internal Internal Conversion Cycle Control CS and SCK SCK CS Continuous Data Output Control CS and SCK SCK CS Internal Connection and Waveforms Figures 5, 6 Figure 7 Figures 8, 9 Figure 10
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Configuration External SCK, Single Cycle Conversion External SCK, 2-Wire I/O Internal SCK, Single Cycle Conversion Internal SCK, 2-Wire I/O, Continuous Conversion
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OSR1 BIT 28 MSB OSR0 BIT 27 BIT 26 BIT 25 BIT 1 BIT 0 LSB Hi-Z
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OSR 64 128 256* 256 512 1024 2048 4096 8192 16384
1.4V 21.8 750nV 22.9 510nV 23.4 375nV 24 250nV 24.4
200nV 24.6 32768**
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APPLICATIO S I FOR ATIO U
4.5V TO 5.5V 1F 2 3 VCC BUSY 15 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR 3-WIRE SPI INTERFACE VCC 200nV NOISE, 50/60Hz REJECTION 10-SPEED/RESOLUTION PROGRAMMABLE 2V NOISE, 880Hz OUTPUT RATE BIT 29 SIG BIT 28 MSB BIT 27 BIT 26 BIT 5 LSB BIT 0 SUB LSB Hi-Z TEST EOC DATA OUTPUT CONVERSION
2440 F05
CS TEST EOC SDO Hi-Z Hi-Z TEST EOC
BIT 31 EOC
SCK (EXTERNAL)
BUSY CONVERSION SLEEP
Figure 5. External Serial Clock, Single Cycle Operation
EOC = 1 (BUSY = 1) while a conversion is in progress and EOC = 0 (BUSY = 0) if the device is in the sleep state. Independent of CS, the device automatically enters the low power sleep state once the conversion is complete. When the device is in the sleep state (EOC = 0), its conversion result is held in an internal static shift register. The device remains in the sleep state until the first rising edge of SCK is seen. Data is shifted out the SDO pin on each falling edge of SCK. This enables external circuitry to latch the output on the rising edge of SCK. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 32nd rising edge of SCK. On the 32nd falling edge of SCK, the device begins a new conversion. SDO goes HIGH (EOC = 1) and BUSY goes HIGH indicating a conversion is in progress. At the conclusion of the data cycle, CS may remain LOW and EOC monitored as an end-of-conversion interrupt. Alternatively, CS may be driven HIGH setting SDO to Hi-Z and BUSY monitored for the completion of a conversion. As described above, CS may be pulled LOW at any time in order to monitor the conversion status on the SDO pin.
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LTC2440 14 REF + FO 13 4 - SCK REF 12 5 SDO IN + ANALOG INPUT RANGE 6 11 -0.5VREF TO 0.5VREF CS IN - 7 SDI 1, 8, 9, 16 10 EXT GND REFERENCE VOLTAGE 0.1V TO VCC
BIT 30
Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the fifth falling edge (SDI must be properly loaded each cycle) and the 32nd falling edge of SCK, see Figure 6. On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring all 32-bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion. External Serial Clock, 2-Wire I/O This timing mode utilizes a 2-wire serial I/O interface. The conversion result is shifted out of the device by an externally generated serial clock (SCK) signal, see Figure 7. CS may be permanently tied to ground, simplifying the user interface or isolation barrier. The external serial clock mode is selected by tying EXT LOW. Since CS is tied LOW, the end-of-conversion (EOC) can be continuously monitored at the SDO pin during the convert and sleep states. Conversely, BUSY (Pin 15) may be used to monitor the status of the conversion cycle. EOC or BUSY may be used as an interrupt to an external controller
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4.5V TO 5.5V 1F 2 3 VCC BUSY 15 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR 3-WIRE SPI INTERFACE VCC 200nV NOISE, 50/60Hz REJECTION 10-SPEED/RESOLUTION PROGRAMMABLE 2V NOISE, 880Hz OUTPUT RATE BIT 31 EOC Hi-Z 1 SCK (EXTERNAL) 5 Hi-Z Hi-Z BIT 30 BIT 29 SIG BIT 28 MSB Hi-Z BIT 27 BIT 9 BIT 8 TEST EOC DATA OUTPUT CONVERSION
2410 F06
CS TEST EOC TEST EOC
BIT 0 SDO EOC
BUSY SLEEP CONVERSION DATA OUTPUT SLEEP
Figure 6. External Serial Clock, Reduced Data Output Length
CS
BIT 31 SDO EOC
SCK (EXTERNAL)
BUSY CONVERSION SLEEP DATA OUTPUT CONVERSION
2440 F07
Figure 7. External Serial Clock, CS = 0 Operation (2-Wire)
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LTC2440 14 REF + FO 13 4 - SCK REF 12 5 SDO IN + ANALOG INPUT RANGE 6 11 -0.5VREF TO 0.5VREF CS IN - 7 SDI 1, 8, 9, 16 10 EXT GND REFERENCE VOLTAGE 0.1V TO VCC
4.5V TO 5.5V 1F 2 3 VCC BUSY 15 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR 3-WIRE SPI INTERFACE VCC 200nV NOISE, 50/60Hz REJECTION 10-SPEED/RESOLUTION PROGRAMMABLE 2V NOISE, 880Hz OUTPUT RATE
LTC2440 14 REF + FO 13 4 - SCK REF 12 5 + SDO IN ANALOG INPUT RANGE 6 11 -0.5VREF TO 0.5VREF CS IN - 7 SDI 1, 8, 9, 16 10 EXT GND REFERENCE VOLTAGE 0.1V TO VCC
BIT 30
BIT 29 SIG
BIT 28 MSB
BIT 27
BIT 26
BIT 5 LSB24
BIT 0
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APPLICATIO S I FOR ATIO U
Once CS is pulled LOW, SCK goes LOW and EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state. Alternatively, BUSY (Pin 15) may be used to monitor the status of the conversion in progress. BUSY is HIGH during the conversion and goes LOW at the conclusion. It remains LOW until the result is read from the device. When testing EOC, if the conversion is complete (EOC = 0), the device will exit the sleep state and enter the data output state if CS remains LOW. In order to prevent the device from exiting the low power sleep state, CS must be pulled HIGH before the first rising edge of SCK. In the internal SCK timing mode, SCK goes HIGH and the device begins outputting data at time tEOCtest after the falling edge of CS (if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW during the falling edge of EOC). The value of tEOCtest is 500ns. If CS is pulled HIGH before time tEOCtest, the device remains in the sleep state. The conversion result is held in the internal static shift register. If CS remains LOW longer than tEOCtest, the first rising edge of SCK will occur and the conversion result is serially shifted out of the SDO pin. The data output cycle begins on
4.5V TO 5.5V 1F 15 BUSY LTC2440 14 3 FO REF + REFERENCE VOLTAGE 13 4 0.1V TO VCC SCK REF - 12 5 SDO IN + ANALOG INPUT RANGE 6 11 -0.5VREF TO 0.5VREF CS IN - 7 SDI 1, 8, 9, 16 10 EXT GND 2 VCC 2440 F08
indicating the conversion result is ready. EOC = 1 (BUSY = 1) while the conversion is in progress and EOC = 0 (BUSY = 0) once the conversion enters the low power sleep state. On the falling edge of EOC/BUSY, the conversion result is loaded into an internal static shift register. The device remains in the sleep state until the first rising edge of SCK. Data is shifted out the SDO pin on each falling edge of SCK enabling external circuitry to latch data on the rising edge of SCK. EOC can be latched on the first rising edge of SCK. On the 32nd falling edge of SCK, SDO and BUSY go HIGH (EOC = 1) indicating a new conversion has begun. Internal Serial Clock, Single Cycle Operation This timing mode uses an internal serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 8. In order to select the internal serial clock timing mode, the EXT pin must be tied HIGH. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter.
BIT 31 EOC
SCK (INTERNAL) BUSY CONVERSION SLEEP
Figure 8. Internal Serial Clock, Single Cycle Operation
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LTC2440
APPLICATIO S I FOR ATIO
this first rising edge of SCK and concludes after the 32nd rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result on the 32nd rising edge of SCK. After the 32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays HIGH and a new conversion starts. Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the first and 32nd rising edge of SCK, see Figure 9. In order to properly select the OSR for the conversion following a data abort, five SCK rising edges must be seen prior to performing a data out abort (pulling CS HIGH). If CS is pulled high prior to the fifth SCK falling edge, the OSR selected depends on the number of SCK signals seen prior to data abort, where subsequent nonaborted conversion cycles return to the programmed OSR. On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion.
4.5V TO 5.5V 1F 2 VCC BUSY 15 14 13 12 11 7 10 VCC = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR 3-WIRE SPI INTERFACE VCC 200nV NOISE, 50/60Hz REJECTION 10-SPEED/RESOLUTION PROGRAMMABLE 2V NOISE, 880Hz OUTPUT RATE
REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE -0.5VREF TO 0.5VREF
> tEOCtest CS TEST EOC TEST EOC
BIT 0 SDO Hi-Z 1 SCK (INTERNAL) 5 EOC Hi-Z
BIT 31 EOC
Hi-Z
Hi-Z
BUSY SLEEP CONVERSION DATA OUTPUT SLEEP DATA OUTPUT CONVERSION
2440 F09
Figure 9. Internal Serial Clock, Reduced Data Output Length
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This is useful for systems not requiring all 32-bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion. Internal Serial Clock, 2-Wire I/O, Continuous Conversion This timing mode uses a 2-wire, all output (SCK and SDO) interface. The conversion result is shifted out of the device by an internally generated serial clock (SCK) signal, see Figure 10. CS may be permanently tied to ground, simplifying the user interface or isolation barrier. The internal serial clock mode is selected by tying EXT HIGH. During the conversion, the SCK and the serial data output pin (SDO) are HIGH (EOC = 1) and BUSY = 1. Once the conversion is complete, SCK, BUSY and SDO go LOW (EOC = 0) indicating the conversion has finished and the device has entered the low power sleep state. The part remains in the sleep state a minimum amount of time (500ns) then immediately begins outputting data. The data output cycle begins on the first rising edge of SCK and
LTC2440 3 FO REF + 4 SCK REF - 5 SDO IN + 6 CS IN - SDI 1, 8, 9, 16 GND EXT BIT 30 BIT 29 SIG BIT 28 MSB Hi-Z BIT 27 BIT 26 BIT 8 TEST EOC
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LTC2440
APPLICATIO S I FOR ATIO U
4.5V TO 5.5V 1F 2 3 VCC BUSY 15 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR 2-WIRE SPI INTERFACE VCC 200nV NOISE, 50/60Hz REJECTION 10-SPEED/RESOLUTION PROGRAMMABLE 2V NOISE, 880Hz OUTPUT RATE VCC BIT 27 BIT 26 BIT 5 LSB24 BIT 0 MSB DATA OUTPUT SLEEP CONVERSION
2410 F10
CS
SDO
BIT 31 EOC
BIT 30
SCK (INTERNAL)
BUSY
CONVERSION
Figure 10. Internal Serial Clock, Continuous Operation
ends after the 32nd rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 32nd rising edge of SCK. After the 32nd rising edge, SDO goes HIGH (EOC = 1) indicating a new conversion is in progress. SCK remains HIGH during the conversion. Normal Mode Rejection and Antialiasing One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2440 significantly simplifies antialiasing filter requirements. The LTC2440's speed/resolution is determined by the over sample ratio (OSR) of the on-chip digital filter. The OSR ranges from 64 for 3.5kHz output rate to 32,768 for 6.9Hz output rate. The value of OSR and the sample rate fS determine the filter characteristics of the device. The first NULL of the digital filter is at fN and multiples of fN where
NORMAL MODE REJECTION (dB)
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LTC2440 14 FO REF + 13 4 - SCK REF 12 5 + SDO IN ANALOG INPUT RANGE 6 11 - -0.5VREF TO 0.5VREF CS IN 7 SDI 1, 8, 9, 16 10 EXT GND REFERENCE VOLTAGE 0.1V TO VCC
BIT 29 SIG
BIT 28
fN = fS/OSR, see Figure 11 and Table 5. The rejection at the frequency fN 14% is better than 80dB, see Figure 12. If FO is grounded, fS is set by the on-chip oscillator at 1.8MHz 5% (over supply and temperature variations). At an OSR of 32,768, the first NULL is at fN = 55Hz and the no latency output rate is fN/8 = 6.9Hz. At the maximum OSR,
0 -20 -40 -60 -80 -100 -120 -140 60 120 240 0 180 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2440 F11
Figure 11. LTC2440 Normal Mode Rejection (Internal Oscillator)
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LTC2440
APPLICATIO S I FOR ATIO
OSR 64 128 256 512 1024 2048 4096 8192 16384 32768* *Simultaneous 50/60 rejection
Table 5. OSR vs Notch Frequency (fN) with Internal Oscillator Running at 9MHz
NOTCH (fN) 28.16kHz 14.08kHz 7.04kHz 3.52kHz 1.76kHz 880Hz 440Hz 220Hz 110Hz 55Hz
-80
NORMAL MODE REJECTION (dB)
NORMAL MODE REJECTION (dB)
-90 -100 -110 -120 -130 -140
47 49 51 53 55 57 59 61 63 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2440 F12
Figure 12. LTC2440 Normal Mode Rejection (Internal Oscillator)
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the noise performance of the device is 200nVRMS with better than 80dB rejection of 50Hz 2% and 60Hz 2%. Since the OSR is large (32,768) the wide band rejection is extremely large and the antialiasing requirements are simple. The first multiple of fS occurs at 55Hz * 32,768 = 1.8MHz, see Figure 13. The first NULL becomes fN = 7.04kHz with an OSR of 256 (an output rate of 880Hz) and FO grounded. While the NULL has shifted, the sample rate remains constant. As a result of constant modulator sampling rate, the linearity, offset and full-scale performance remains unchanged as does the first multiple of fS.
0 -20 -40 -60 1.8MHz -80 -100 REJECTION > 120dB -120 -140 1000000 2000000 0 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
1440 F13
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Figure 13. LTC2440 Normal Mode Rejection (Internal Oscillator)
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LTC2440
APPLICATIO S I FOR ATIO
The sample rate fS and NULL fN, my also be adjusted by driving the FO pin with an external oscillator. The sample rate is fS = fEOSC/5, where fEOSC is the frequency of the clock applied to FO. Combining a large OSR with a reduced sample rate leads to notch frequencies fN near DC while maintaining simple antialiasing requirements. A 100kHz clock applied to FO results in a NULL at 0.6Hz plus all harmonics up to 20kHz, see Figure 14. This is useful in applications requiring digitalization of the DC component of a noisy input signal and eliminates the need of placing a 0.6Hz filter in front of the ADC. An external oscillator operating from 100kHz to 20MHz can be implemented using the LTC1799 (resistor set SOT-23 oscillator), see Figure 22. By floating pin 4 (DIV) of the LTC1799, the output oscillator frequency is:
10k fOSC = 10MHz * 10 * RSET
The normal mode rejection characteristic shown in Figure 14 is achieved by applying the output of the LTC1799 (with RSET = 100k) to the FO pin on the LTC2440 with SDI tied HIGH (OSR = 32768).
0
NORMAL MODE REJECTION (dB)
-20 -40 -60 -80 -100 -120 -140 2 4 6 10 0 8 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2440 F14
Figure 14. LTC2440 Normal Mode Rejection (External Oscillator at 90kHz)
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Reduced Power Operation In addition to adjusting the speed/resolution of the LTC2440, the speed/resolution/power dissipation may also be adjusted using the automatic sleep mode. During the conversion cycle, the LTC2440 draws 8mA supply current independent of the programmed speed. Once the conversion cycle is completed, the device automatically enters a low power sleep state drawing 8A. The device remains in this state as long as CS is HIGH and data is not shifted out. By adjusting the duration of the sleep state (hold CS HIGH longer) and the duration of the conversion cycle (programming OSR) the DC power dissipation can be reduced, see Figure 16. For example, if the OSR is programmed at the fastest rate (OSR = 64, tCONV = 0.285ms) and the sleep state is 10ms, the effective output rate is approximately 100Hz while the average supply current is reduced to 240A. By further extending the sleep state to 100ms, the effective output rate of 10Hz draws on average 30A. Noise, power, and speed can be optimized by adjusting the OSR (Noise/ Speed) and sleep mode duration (Power).
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LTC2440
APPLICATIO S I FOR ATIO
CONVERTER STATE SLEEP DATA OUT CS CONVERT
SUPPLY CURRENT
8A
8mA
Figure 15. Reduced Power Timing Mode
LTC2440 Input Structure Modern delta sigma converters have switched capacitor front ends that repeatedly sample the input voltage over some time period. The sampling process produces a small current pulse at the input and reference terminals as the capacitors are charged. The LTC2440 switches the input and reference to a 5pF sample capacitor at a frequency of 1.8MHz. A simplified equivalent circuit is shown in Figure 16. The average input and reference currents can be expressed in terms of the equivalent input resistance of the sample capacitor, where: Req = 1/(fSW * Ceq)
IREF+ VREF+ ILEAK IIN+ VIN+ ILEAK IIN - VIN - ILEAK IREF - VREF - ILEAK VCC ILEAK VCC ILEAK VCC ILEAK VCC ILEAK
SWITCHING FREQUENCY fSW = 1.8MHz INTERNAL OSCILLATOR fSW = fEOSC/5 EXTERNAL OSCILLATOR
Figure 16. LTC2440 Input Structure
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SLEEP DATA OUT CONVERT SLEEP 8A 8mA 8A
2440 F15
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When using the internal oscillator, fSW is 1.8MHz and the equivalent resistance is approximately 110k. Driving the Input and Reference Because of the small current pulses, excessive lead length at the analog or reference input may allow reflections or ringing to occur, affecting the conversion accuracy. The key to preserving the accuracy of the LTC2440 is complete settling of these sampling glitches at both the input and reference terminals. There are several recommended methods of doing this.
RSW (TYP) 500
RSW (TYP) 500 CEQ 5pF (TYP) (CEQ = 3.5pF SAMPLE CAP + PARASITICS)
RSW (TYP) 500
RSW (TYP) 500
2440 F16
LTC2440
APPLICATIO S I FOR ATIO
Direct Connection to Low Impedance Sources If the ADC can be located physically close to the sensor, it can be directly connected to sensors or other sources with impedances up to 350 with no other components required (see Figure 17).
4.5V to 5.5V
IN +
REF + LTC2440
IN
-
REF -
2440 F17
Figure 17. Direct Connection to Low Impedance (<350) Source is Possible if the Sensor is Located Close to the ADC.
Longer Connections to Low Impedance Sources If longer lead lengths are unavoidable, adding an input capacitor close to the ADC input pins will average the charging pulses and prevent reflections or ringing (see Figure 18). Averaging the current pulses results in a DC input current that should be taken into account. The resulting 110k input impedance will result in a gain error of 0.44% for a 350 bridge (within the full scale specs of many bridges) and a very low 12.6ppm error for a 2 thermocouple connection.
4.5V to 5.5V 1F 1F IN + VREF+ LTC2440 IN - REMOTE THERMOCOUPLE 1F GND
2440 F18
VCC
Figure 18. Input Capacitors Allow Longer Connection Between the Low Impedance Source and the ADC.
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Buffering the LTC2440 Many applications will require buffering, particularly where high impedance sources are involved or where the device being measured is located some distance from the LTC2440. When buffering the LTC2440 a few simple steps should be followed. Figure 19 shows a network suitable for coupling the inputs of a LTC2440 to a LTC2051 chopper-stabilized op amp. The 3V offset and low noise of the LTC2051 make it a good choice for buffering the LTC2440. Many other op amps will work, with varying performance characteristics. The LTC2051 is configured to be able to drive the 1F capacitors at the inputs of the LTC2440. The 1F capacitors should be located close to the ADC input pins. The measured total unadjusted error of Figure 19 is well within the specifications of the LTC2440 by itself. Most autozero amplifiers will degrade the overall resolution to some degree because of the extremely low input noise of the LTC2440, however the LTC2051 is a good general purpose buffer. The measured input referred noise of two LTC2051s buffering both LTC2440 inputs is approximately double that of the LTC2440 by itself, which reduces the effective resolution by 1-bit for all oversample ratios. Adding gain to the LTC2051 will increase gain and offset errors and will not appreciably increase the overall resolution, so it has limited benefit. Procedure For Coupling Any Amplifier to the LTC2440 The LTC2051 is suitable for a wide range of DC and low frequency measurement applications. If another amplifier is to be selected, a general procedure for evaluating the suitability of an amplifier for use with the LTC2440 is suggested here: 1. Perform a thorough error and noise analysis on the amplifier and gain setting components to verify that the amplifier will perform as intended. 2. Measure the large signal response of the overall circuit. The capacitive load may affect the maximum slew rate of the amplifier. Verify that the slew rate is adequate for the
1F
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LTC2440
APPLICATIO S I FOR ATIO
fastest expected input signal. Figure 20 shows the large signal response of the circuit in Figure 19. 3. Measure noise performance of the complete circuit. A good technique is to build one amplifier for each input, even if only one will be used in the end application. Bias both amplifier outputs to midscale, with the inputs tied together. Verify that the noise is as expected, taking into account the bandwidth of the LTC2440 inputs for the OSR being used, the amplifier's broadband voltage noise and 1/f corner (if any) and any additional noise due to the amplifier's current noise and source resistance.
8-12V LT1236-5
5k C1 R1 0.01F 10 R2
1
-
IN+
+
/2 LTC2051HV 5k C4 R4 0.01F 10 R5 C5 1F
-
IN-
+
1/ LTC2051HV 2
Figure 19. Buffering the LTC2440 from High Impedance Sources Using A Chopper Amplifier
100mV/DIV
100s/DIV
2440 F20
2mV/DIV
Figure 20. Large Signal Input Settling Time Indicates Completed Settling with Selected Load Capacitance.
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For more information on testing high linearity ADCs, refer to Linear Technology Design Solutions 11. Input Bandwidth and Frequency Rejection The combined effect of the internal SINC4 digital filter and the digital and analog autocalibration circuits determines the LTC2440 input bandwidth and rejection characteristics. The digital filter's response can be adjusted by setting the oversample ratio (OSR) through the SPI interface or by supplying an external conversion clock to the FO pin. Table 6 lists the properties of the LTC2440 with various
5V 4.7F 0.01F 10F VCC REF + BUSY 15 14 0.1F C2 1F FO LTC2440 13 - SCK REF 12 SDO 11 5 + CS IN 7 6 - IN SDI 1, 8, 9, 16 10 EXT 4
2440 F19
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C2, C5 TAIYO YUDEN JMK107BJ105MA
5ns/DIV
2440 F21
Figure 21. Dynamic Input Current is Attenuated by Load Capacitance and Completly Settled Before the Next Conversion Sample Resulting in No Reduction in Performance.
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LTC2440
APPLICATIO S I FOR ATIO
combinations of oversample ratio and clock frequency. Understanding these properties is the key to fine tuning the characteristics of the LTC2440 to the application. Maximum Conversion Rate The maximum conversion rate is the fastest possible rate at which conversions can be performed. First Notch Frequency This is the first notch in the SINC4 portion of the digital filter and depends on the fo clock frequency and the oversample ratio. Rejection at this frequency and its
Table 6
Oversample Ratio
(OSR)
ADC
Noise*
ENOB
(VREF = 5V)*
Maximum Conversion Rate
Internal 9MHz clock External fo
64 128 256 512 1024 2048 4096 8192 16384 32768
23V 3.5V 2V 1.4V 1V 750nV 510nV 375nV 250nV 200nV
17 20 21.3 21.8 22.4 22.9 23.4 24 24.4 24.6
3515.6 1757.8 878.9 439.5 219.7 109.9 54.9 27.5 13.7 6.9
Fo/2560 Fo/5120 Fo/10240 Fo/20480 Fo/40960 Fo/81920 Fo/163840 Fo/327680 Fo/655360 Fo/1310720
*ADC noise increases by approximately 2 when OSR is decreased by a factor of 2 for OSR 32768 to OSR 256. The ADC noise at OSR 128 and OSR 64 include effects from internal modulator quantization noise.
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multiples (up to the modulator sample rate of 1.8MHz) exceeds 120dB. This is 8 times the maximum conversion rate. Effective Noise Bandwidth The LTC2440 has extremely good input noise rejection from the first notch frequency all the way out to the modulator sample rate (typically 1.8MHz). Effective noise bandwidth is a measure of how the ADC will reject wideband input noise up to the modulator sample rate. The example on the following page shows how the noise rejection of the LTC2440 reduces the effective noise of an amplifier driving its input.
First Notch Frequency
Internal 9MHz clock External fo
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Effective Noise BW
Internal 9MHz clock External fo
-3dB point(Hz)
Internal 9MHz clock External fo
28125 14062.5 7031.3 3515.6 1757.8 878.9 439.5 219.7 109.9 54.9
Fo/320 Fo/640 Fo/1280 Fo/2560 Fo/5120 Fo/1020 Fo/2050 Fo/4100 Fo/8190 Fo/16380
3148 1574 787 394 197 98.4 49.2 24.6 12.4 6.2
Fo/2850 Fo/5700 Fo/11400 Fo/22800 Fo/45700 Fo/91400 Fo/183000 Fo/366000 Fo/731000 Fo/1463000
1696 848 424 212 106 53 26.5 13.2 6.6 3.3
Fo/5310 Fo/10600 Fo/21200 Fo/42500 Fo/84900 Fo/170000 Fo/340000 Fo/679000 Fo/1358000 Fo/2717000
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LTC2440
APPLICATIO S I FOR ATIO
Example:
If an amplifier (e.g. LT1219) driving the input of an LTC2440 has wideband noise of 33nV/Hz, band-limited to 1.8MHz, the total noise entering the ADC input is: 33nV/Hz * 1.8MHz = 44.3V. When the ADC digitizes the input, its digital filter filters out the wideband noise from the input signal. The noise reduction depends on the oversample ratio which defines the effective bandwidth of the digital filter. At an oversample of 256, the noise bandwidth of the ADC is 787Hz which reduces the total amplifier noise to: 33nV/Hz * 787Hz = 0.93V. The total noise is the RMS sum of this noise with the 2V noise of the ADC at OSR=256. 0.93V2 + 2uV2 = 2.2V. Increasing the oversampling ratio to 32768 reduces the noise bandwidth of the ADC to 6.2Hz which reduces the total amplifier noise to: 33nV/Hz * 6.2Hz = 82nV.
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The total noise is the RMS sum of this noise with the 200nV noise of the ADC at OSR = 32768. 82nV2 + 2V2 = 216nV. In this way, the digital filter with its variable oversampling ratio can greatly reduce the effects of external noise sources. Using Non-Autozeroed Amplifiers for Lowest Noise Applications Ultralow noise applications may require the use of low noise bipolar amplifiers that are not autozeroed. Because the LTC2440 has such exceptionally low offset, offset drift and 1/f noise, the offset drift and 1/f noise in the amplifiers may need to be compensated for to retain the system performance of which the ADC is capable. The circuit of Figure 23 uses low noise bipolar amplifiers and correlated double sampling to achieve a resolution of 14nV, or 19 effective bits over a 10mV span. Each measurement is the difference between two ADC readings taken with opposite polarity bridge excitation. This cancels 1/f noise below 3.4Hz and eliminates errors due to parasitic thermocouples. Allow 750s settling time after switching excitation polarity.
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LTC2440
PACKAGE DESCRIPTIO
.254 MIN
.0165 .0015
RECOMMENDED SOLDER PAD LAYOUT
.007 - .0098 (0.178 - 0.249)
.016 - .050 (0.406 - 1.270)
NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
TYPICAL APPLICATIO S
4.5V TO 5.5V 1F 15 BUSY LTC2440 14 3 FO REF + REFERENCE VOLTAGE 13 4 0.1V TO VCC SCK REF - 12 5 + SDO IN ANALOG INPUT RANGE 6 11 -0.5VREF TO 0.5VREF CS IN - 7 VCC SDI 1, 8, 9, 16 10 EXT GND VCC 2 LTC1799 50 5 OUT V+ 1 RSET
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 .005
.189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9
.009 (0.229) REF
.150 - .165
.229 - .244 (5.817 - 6.198)
.150 - .157** (3.810 - 3.988)
.0250 TYP
1
23
4
56
7
8
.004 - .0098 (0.102 - 0.249)
.015 .004 x 45 (0.38 0.10)
0 - 8 TYP
.053 - .068 (1.351 - 1.727)
.008 - .012 (0.203 - 0.305)
.0250 (0.635) BSC
GN16 (SSOP) 0502
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0.1F 3-WIRE SPI INTERFACE GND 2
NC
4
DIV
SET
3
2440 TA05
Figure 22. Simple External Clock Source
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LTC2440
TYPICAL APPLICATIO S
VREF 100k 3 +7V TOP_P LT1461-5 10F 0.1F VREF 4 5,6,7,8 2 1
100k
VREF 100k 3
4 5,6,7,8 2 1
2X SILICONIX SI9801 BOTTOM_N
100k
Figure 23. Bridge Reversal Eliminates 1/f Noise and Offset Drift of a Low Noise, Non-autozeroed, Bipolar Amplifier. Circuit Gives 14nV Noise Level or 19 Effective Bits Over a 10mV Span
RELATED PARTS
PART NUMBER LT1025 LTC1043 LTC1050 LT1236A-5 LT1461 LTC1592 LTC1655 LTC1799 LTC2053 LTC2400 LTC2401/LTC2402 LTC2404/LTC2408 LTC2410/LTC2413 LTC2411 LTC2420LTC2424/ LTC2428 DESCRIPTION Micropower Thermocouple Cold Junction Compensator Dual Precision Instrumentation Switched Capacitor Building Block Precision Chopper Stabilized Op Amp Precision Bandgap Reference, 5V Micropower Series Reference, 2.5V Ultraprecise 16-Bit SoftSpan DAC 16-Bit Rail-to-Rail Micropower DAC Resistor Set SOT-23 Oscillator Rail-to-Rail Instrumentation Amplifier 24-Bit, No Latency ADC in SO-8 1-/2-Channel, 24-Bit, No Latency ADC in MSOP 4-/8-Channel, 24-Bit, No Latency ADC 24-Bit, No Latency ADC 24-Bit, No Latency ADC in MSOP 1-/4-/8-Channel, 20-Bit, No Latency ADCs
TM
SoftSpan is a trademark of Linear Technology Corporation.
28
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
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TOP_N
+
2X LT1677
10 4 REF + 1k 0.1% 1F IN + LTC2440 1k 0.1% 1F IN - REF - 10
-
0.047F
100 0.1%
- +
BOTTOM_P
0.047F
2440 F22
COMMENTS 80A Supply Current, 0.5C Initial Accuracy Precise Charge, Balanced Switching, Low Power No External Components 5V Offset, 1.6VP-P Noise 0.05% Max, 5ppm/C Drift 0.04% Max, 3ppm/C Max Drift Six Programmable Output Ranges 1LSB DNL, 600A, Internal Reference, SO-8 Single Resistor Frequency Set 10V Offset with 50nV/C Drift, 2.5VP-P Noise 0.01Hz to 10Hz 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A 0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A 800nVRMS Noise, 5ppm INL/Simultaneous 50Hz/60Hz Rejection 1.45VRMS Noise, 6ppm INL 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400/ LTC2404/LTC2408
sn2440, 2440fas LT/TP 0105 REV A * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2002

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